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| PRELIMINARY PRODUCT SPECIFICATIONS (R) Integrated Circuits Group 256M (x16) Boot Block Flash and 32M (x16) SCRAM (Model No.: LRS1830) Stacked Chip LRS1830 Spec No.: EL14Z046 Issue Date: January 14, 2003 sharp L R S1 8 3 0 Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * * * * * * Office electronics Instrumentation and measuring equipment Machine tools Audiovisual equipment Home appliance Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trains, automobiles, and other transportation equipment * Mainframe computers * Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment * Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * * * * Aerospace equipment Communications equipment for trunk lines Control equipment for the nuclear power industry Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. Please direct all queries regarding the products covered herein to a sales representative of the company. sharp L R S1 8 3 0 1 Contents 1. Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6. Flash Memory 1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1.1 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1.2 Simultaneous Operation Modes Allowed with Four Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.1 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.2 Identifier Codes for Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.3 Functions of Block Lock and Block Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2.4 Block Locking State Transitions upon Command Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2.5 Block Locking State Transitions upon WP/ACC Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 6.4 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4.1 Memory Map - F1 Selected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4.2 Memory Map - F2 Selected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 6.6 DC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6.1 AC Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6.3 Write Cycle (WE / F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.6.4 Block Erase, Bank Erase, (Page Buffer) Program Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.6.5 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6.6 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7. Smartcombo RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 7.2 7.3 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.1 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC Electrical Characteristics for Smartcombo RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AC Electrical Characteristic for Smartcombo RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.1 AC Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.4 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3.5 Sleep Mode Entry / Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 sharp 7.4 7.5 7.6 L R S1 8 3 0 2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Page Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5.1 Features of Page Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Mode Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6.1 Mode Register Setting Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6.2 Cautions for Setting Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.7 Smartcombo RAM AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8. Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9. Flash Memory Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11. Related Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12. Package and Packing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 sharp L R S1 8 3 0 3 1. Description The LRS1830 is a combination memory organized as 8,388,608 x16 bit flash memory, 8,388,608 x16 bit flash memory and 2,097,152 x16 bit Smartcombo RAM in one package. Features -Power supply **** 2.7V to 3.1V -Operating temperature **** -30C to +85C -Not designed or rated as radiation hardened -115 pin (LCSP115-P-0914) plastic package -Flash memory has P-type bulk silicon, and Smartcombo RAM has P-type bulk silicon -For specifications of Flash memory and Smartcombo RAM, refer to specification of each chip Flash Memory 1 (F1: 128M (x16) bit Flash Memory) -Access Time (tAVQV) -Power supply current (The current for F1-VCC pin) Read Word write Block erase Standby Flash Memory 2 (F2: 128M (x16) bit Flash Memory) -Access Time (tAVQV) -Power supply current (The current for F2-VCC pin) Read Word write Block erase Standby Smartcombo RAM (32M (x16) bit Smartcombo RAM) -Access Time (tAA) -Cycle time -Power Supply current Operating current **** * * * * * * * * * * * * * * * * 70 ns 30 mA 120 mA 60 mA 40 A (Max.) (Max. tCYCLE = 200ns, CMOS Input) (Max.) (Max.) (Max. F2-CE = F2-RST = F2-VCC 0.2V) **** * * * * * * * * * * * * * * * * 70 ns 30 mA 120 mA 60 mA 40 A (Max.) (Max. tCYCLE = 200ns, CMOS Input) (Max.) (Max.) (Max.) **** **** **** 70 ns 70 ns 50 mA (Max.) (Min.) (Max. tRC, tWC = Min.) sharp 2. Pin Configuration L R S1 8 3 0 4 INDEX (TOP View) 1 A DU B DU 2 DU DU 3 DU DU DU DU DU 4 DU DU A11 A8 5 DU 6 DU 7 DU BS A14 A10 DU 8 DU A16 DU 9 DU DU 10 DU GND 11 DU DU 12 DU DU DU DU DU 13 DU DU 14 DU DU A15 F-A21 A12 A19 A13 A9 C D E F G H DQ15 DQ7 DQ14 DQ6 DQ13 DQ12 DQ5 DU DU DQ1 GND A0 DU DQ4 SC-VCC DU WE SC-CE2 A20 F1F2-CE WP/ACC F1-RST RY/BY DU F2RY/BY GND DU DU DU DU LB A7 DU DU UB A6 A3 DU A18 A5 A2 DU A17 A4 A1 DU DQ3 F1-VCC DQ11 F2-VCC DQ9 DQ10 DQ2 GND OE DQ0 DQ8 F2-RST DU DU DU DU DU DU J F1-CE SC-CE1 DU DU DU DU K DU Note) Do not float any GND pins. sharp L R S1 8 3 0 5 Pin A0 to A20 F-A21 BS (A22) F1-CE F2-CE SC-CE1 SC-CE2 WE OE LB UB Address Inputs (Common) Address Input (Flash) Description Type Input Input Input Input Input Input Bank Select (Flash) Bank 0 is selected by BS = "0". Bank 1 is selected by BS = "1". This pin can be used for A22 pin. Refer to AC Characteristics for timings. Chip Enable Input (Flash - F1 Selected) Chip Enable Input (Flash - F2 Selected) Chip Enable Input (Smartcombo RAM) Sleep State Input (Smartcombo RAM) Write Enable Input (Common) Output Enable Input (Common) Byte Enable Input : DQ0 to DQ7 (Smartcombo RAM) Byte Enable Input : DQ8 to DQ15 (Smartcombo RAM) Reset Power Down Input (Flash - F1 Selected) Block erase and Write : VIH Read : VIH Reset Power Down : VIL Reset Power Down Input (Flash - F2 Selected) Block erase and Write : VIH Read : VIH Reset Power Down : VIL Write Protect Input (Flash) When WP/ACC is VIL, locked-down blocks cannot be unlocked. Erase or program operation can be executed to the blocks which are not locked and locked-down. When WP/ACC is VIH, lock-down is disabled. Moreover, High Speed Erase and High Speed Program can be operated by applying 12V 0.3V to WP/ACC. In this case, WP/ACC becomes the power supply pin. * See Chapter B-1 Input Input Input Input Input F1-RST Input F2-RST Input WP/ACC Input / Power F1-RY/BY Ready/Busy Output (Flash - F1 Selected) During an Erase or Write operation : VOL Block Erase and Write Suspend : High-Z (High impedance) Ready/Busy Output (Flash - F2 Selected) During an Erase or Write operation : VOL Block Erase and Write Suspend : High-Z (High impedance) Data Inputs and Outputs (Common) Power Supply (Flash - F1 Selected) Power Supply (Flash - F2 Selected) Power Supply (Smartcombo RAM) GND (Common) Don't Use Open Drain Output Open Drain Output Input / Output Power Power Power Power - F2-RY/BY DQ0 to DQ15 F1-VCC F2-VCC SC-VCC GND DU sharp 3. Block Diagram L R S1 8 3 0 6 A0 to A20 OE, WE BS F-A21 WP/ACC F1-CE F1-RST F1: 128M (x16) bit Flash memory F1-RY/BY F1-VCC F2: 128M (x16) bit Flash memory F2-CE F2-RST F2-RY/BY F2-VCC DQ0 to DQ15 SC-CE1 SC-CE2 LB UB 32M (x16) bit Smartcombo RAM SC-VCC GND Note: Only one among F1-CE, F2-CE and SC-CE1 can be low. Two or more should not be low. sharp 4. Absolute Maximum Ratings Symbol VCC VIN TA TSTG WP/ACC Notes: Parameter Supply Voltage Input Voltage Operating Temperature Storage Temperature WP/ACC Voltage L R S1 8 3 0 7 Notes 1 1,2,3,4 -0.2 -0.4 -30 -55 1,3,5 -0.2 Ratings to to to to to +3.6 VCC +0.3 +85 +125 +12.6 Unit V V C C V 1. The maximum applicable voltage on any pins with respect to GND. 2. Except WP/ACC. 3. -1.0V undershoot is allowed when the pulse width is less than 5 nsec. 4. VIN should not be over VCC +0.3V. 5. Applying 12V 0.3V to WP/ACC during erase/write can only be done for a maximum of 1000 cycles on each block. WP/ACC may be connected to 12V 0.3V for total of 80 hours maximum. +13.0V overshoot is allowed when the pulse width is less than 20 nsec. 5. Recommended DC Operating Conditions (TA = -30C to +85C) Symbol VCC WP/ACC VIL VIH Notes: 1. VCC is the lower of F1-VCC, F2-VCC or SC-VCC. 2. VCC includes both F1-VCC, F2-VCC and SC-VCC. Parameter Supply Voltage WP/ACC Voltage when Used as a Logic Control Supply Voltage Input Voltage Input Voltage VIL VIH Notes 2 Min. 2.7 -0.4 2.4 11.7 -0.4 2.4 12 Typ. Max. 3.1 0.4 VCC +0.4 (1) 12.3 0.4 VCC +0.4 (1) Unit V V V V V V sharp 6. Flash Memory 1, 2 6.1 Truth Table 6.1.1 Bus Operation (1) Flash Read Output Disable Write Standby Reset Power Down Notes: Notes 3,5 5 2,3,4,5 5 5,6 H X L L R S1 8 3 0 8 F-CE F-RST OE L WE H L DQ0 to DQ15 (8) High - Z H H DIN High - Z H L X X 1. L = VIL, H = VIH, X = H or L, High-Z = High impedance. Refer to the DC Characteristics. 2. Command writes involving block erase, (page buffer) program are reliably executed when WP/ACC = VACCH1/2 and VCC = 2.7V to 3.1V. Command writes involving bank erase is reliably executed when WP/ACC = VACCH1 and VCC = 2.7V to 3.1V. Block erase, bank erase, (page buffer) program with WP/ACC < VACCH1/2 (Min.) produce spurious results and should not be attempted. 3. Never hold OE low and WE low at the same timing. 4. Refer to Section 6.2 Command Definitions for Flash Memory valid DIN during a write operation. 5. WP/ACC set to VIL or VIH. 6. Electricity consumption of Flash Memory is lowest when F-RST = GND 0.2V. 7. Never hold F1-CE low and F2-CE low at the same timing. 8. Flash Read Mode Mode Read Array Address X See 6.2.2 DQ0 to DQ15 DOUT See 6.2.2 Read Identifier Codes Read Query Refer to the Appendix Refer to the Appendix sharp L R S1 8 3 0 9 6.1.2 Simultaneous Operation Modes Allowed with Four Planes (1, 2, 3, 4) THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE PARTITION IS: Read Array Read ID Read Status Read Query Word Program Page Buffer Program Block Erase Bank Erase Program Suspend Block Erase Suspend Notes: 1. "X" denotes the operation available. 2. Configurative Partition Dual Work Restrictions: Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition. Only one partition can be erased or programmed at a time - no command queuing. Commands must be written to an address within the block targeted by that command. 3. This table shows operation which can be performed by only the selected chip, not during 2 chips of F1 and F2. 4. It is inhibited to execute the dual work operation between the memory area selected by BS="0" and the memory area selected by BS="1" X X X X Read Array X X X X X X X Read ID X X X X X X X Read Status X X X X X X X X X X X X X X X X Read Query X X X X X X X Word Program X X X X Page Buffer Program X X X X Block Erase X X X X X Bank Erase Program Suspend X X X X Block Erase Suspend X X X X X X sharp 6.2 Command Definitions for Flash Memory (11) 6.2.1 Command Definitions Command Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Block Erase Bank Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock Bit Clear Block Lock Bit Set Block Lock-down Bit Set Partition Configuration Register Notes: 1. Bus operations are defined in 6.1.1 Bus Operation. Bus Cycles Req'd 1 2 2 2 1 2 2 2 4 1 1 2 2 2 2 12 10 5 5, 9 5, 6 5, 7 8, 9 8, 9 4 4 L R S1 8 3 0 10 First Bus Cycle Notes Oper (1) Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address (2) PA PA PA PA PA BA X WA WA PA PA BA BA BA PCRC Data FFH 90H 98H 70H 50H 20H 30H 40H or 10H E8H B0H D0H 60H 60H 60H 60H Write Write Write Write Write Write Write Write Read Read Read Second Bus Cycle Oper (1) Address (2) IA QA PA BA X WA WA Data (3) ID QD SRD D0H D0H WD N-1 BA BA BA PCRC 01H D0H 2FH 04H 2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle. X=Any valid address within the device. Bank erase is executed to the bank selected by BS. PA=Address within the selected partition. IA=Identifier codes address (See 6.2.2 Identifier Codes for Read Operation). QA=Query codes address. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. PCRC=Partition configuration register code presented on the address A0-A15. 3. ID=Data read from identifier codes (See 6.2.2 Identifier Codes for Read Operation). QD=Data read from query database. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details. SRD=Data read from status register. See 6.3 Register Definition for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the rising edge of WE or CE (whichever goes high first) during command write cycles. N-1=N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code (See 6.2.2 Identifier Codes for Read Operation). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, bank erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when F-RST is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any valid address within the target block to be programmed and the confirm command (D0H). Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details. sharp L R S1 8 3 0 11 8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. Bank erase operation can not be suspended. 10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP/ACC is VIL. When WP/ACC is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. 12. The partition setting for the memory area which consists of Plane0-Plane3 can be configured by writing the Set Partition Configuration Register command with BS="0". The partition setting for the memory area which consists of Plane4-Plane7 can be configured by writing the Set Partition Configuration Register command with BS="1". sharp L R S1 8 3 0 12 6.2.2 Identifier Codes for Read Operation Code Manufacturer Code Device Code Manufacturer Code Device Code Block is Unlocked Block is Locked Block Lock Configuration Code Block is not Locked-Down Block is Locked-Down Device Configuration Code Notes: 1. Block Address = The beginning location of a block address within the partition to which the Read Identifier Codes command (90H) has been written. DQ15-DQ2 is reserved for future implementation. 2. PCRC = Partition Configuration Register Code. 3. The address A21-A16 are shown in below table for reading the manufacturer, device, device configuration code. The address to read the identifier codes is dependent on the partition which is selected when writing the Read Identifier Codes command (90H). See Partition Configuration Register Definition (P.18) for the partition configuration register. Identifier Codes for Read Operation on Partition Configuration (128M (x16)-bit device) Address (128M (x16)-bit device) Partition Configuration Register BS="0" PCR.10 0 0 0 1 0 1 1 1 PCR.9 0 0 1 0 1 1 0 1 PCR.8 0 1 0 0 1 0 1 1 00H 00H or 10H 00H or 20H 00H or 30H 00H or 10H or 20H 00H or 20H or 30H 00H or 10H or 30H 00H or 10H or 20H or 30H [A21-A16] 00H 00H or 10H 00H or 20H 00H or 30H 00H or 10H or 20H 00H or 20H or 30H 00H or 10H or 30H 00H or 10H or 20H or 30H BS="1" [A21-A16] Partition Configuration Register 0006H Block Address +2 Address [A15-A0] 0000H 0001H Data [DQ15-DQ0] 00B0H 0008H DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 PCRC Notes 3 3 1 1 1 1 2, 3 sharp L R S1 8 3 0 13 6.2.3 Functions of Block Lock and Block Lock-Down Current State State [000] [001](3) [011] [100] [101](3) [110](4) [111] Notes: 1. DQ0 = 1: a block is locked; DQ0 = 0: a block is unlocked. DQ1 = 1: a block is locked-down; DQ1 = 0: a block is not locked-down. 2. Erase and program are general terms, respectively, to express: block erase, bank erase and (page buffer) program operations. 3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (WP/ACC = "0") or [101] (WP/ACC = "1"), regardless of the states before power-off or reset operation. 4. When WP/ACC is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 6.2.4 Block Locking State Transitions upon Command Write (4) Current State State [000] [001] [011] [100] [101] [110] [111] Notes: 1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lockdown" means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0 = 0), the corresponding block is locked-down and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written. 4. In this state transitions table, assumes that WP/ACC is not changed and fixed VIL or VIH. WP/ACC 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 Result after Lock Command Written (Next State) Set Lock (1) [001] No Change (3) No Change [101] No Change [111] No Change Clear Lock (1) No Change [000] No Change No Change [100] No Change [110] Set Lock-down (1) [011] (2) [011] No Change [111] (2) [111] [111] (2) No Change WP/ACC 0 0 0 1 1 1 1 DQ1(1) 0 0 1 0 0 1 1 DQ0(1) 0 1 1 0 1 0 1 Unlocked Locked Locked-down Unlocked Locked Lock-down Disable Lock-down Disable State Name Erase/Program Allowed (2) Yes No No Yes No Yes No sharp L R S1 8 3 0 14 6.2.5 Block Locking State Transitions upon WP/ACC Transition (4) Current State Previous State State [110] (2) Result after WP/ACC Transition (Next State) DQ0 0 1 1 0 1 0 1 WP/ACC = 0 1 (1) [100] [101] [110] WP/ACC = 1 0 (1) [000] [001] [011] (3) [011] WP/ACC 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 [000] [001] [011] [100] [101] [110] [111] Other than [110] (2) Notes: [111] - 1. "WP/ACC = 0 1" means that WP/ACC is driven to VIH and "WP/ACC = 1 0" means that WP/ACC is driven to VIL. 2. State transition from the current state [011] to the next state depends on the previous state. 3. When WP/ACC is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. sharp 6.3 Register Definition L R S1 8 3 0 15 Status Register Definition R R R 15 14 13 WSMS BESS BEFCES 7 6 5 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) R 12 PBPS 4 R 11 WPACCS 3 Notes: Status Register indicates the status of the partition, not WSM (Write State Machine). Even if the SR.7 is "1", the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. R 10 PBPSS 2 R 9 DPS 1 R 8 R 0 SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND BANK ERASE STATUS (BEFCES) 1 = Error in Block Erase or Bank Erase 0 = Successful Block Erase or Bank Erase SR.4 = (PAGE BUFFER) PROGRAM STATUS (PBPS) 1 = Error in (Page Buffer) Program 0 = Successful (Page Buffer) Program SR.3 = WP/ACC STATUS (WPACCS) 1 = 3.1V < WP/ACC < 11.7V Detect, Operation Abort 0 = WP/ACC OK SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 =RESERVED FOR FUTURE ENHANCEMENTS (R) Check SR.7 or F-RY/BY to determine block erase, bank erase, (page buffer) program completion. SR.6 - SR.1 are invalid while SR.7= "0". If both SR.5 and SR.4 are "1"s after a block erase, bank erase, (page buffer) program, set/clear block lock bit, set block lockdown bit or set partition configuration register attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of WP/ACC level. The WSM interrogates and indicates the WP/ACC level only after Block Erase, Bank Erase, (Page Buffer) Program command sequences. SR.3 is not guaranteed to report accurate feedback when WP/ACC VACCH1/2. SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Bank Erase, (Page Buffer) Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes command indicates block lock bit status. SR.15 - SR.8, SR.3 and SR.0 are reserved for future use and should be masked out when polling the status register. sharp L R S1 8 3 0 16 Extended Status Register Definition R 15 SMS 7 R 14 R 6 R 13 R 5 R 12 R 4 Notes: XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 =STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not. R 11 R 3 R 10 R 2 R 9 R 1 R 8 R 0 XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register. sharp L R S1 8 3 0 17 Partition Configuration Register Definition R 15 R 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 PC2 10 R 2 PC1 9 R 1 PC0 8 R 0 PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in Bank 0 selected by BS="0") 010 = Plane 0-1 and Plane2-3 are merged into one partition respectively. 100 = Plane 0-2 are merged into one partition. (default in Bank 1 selected by BS="1") 011 = Plane 2-3 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 110 = Plane 0-1 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 101 = Plane 1-2 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 111 = There are four partitions in this configuration. Each plane corresponds to each partition respectively. Dual work operation is available between any two partitions. PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) Notes: After power-up or device reset, PCR10-8 (PC2-0) is set to "001" in Bank 0 and "100" in Bank 1. See the table below for more details. PCR.15-11 and PCR.7-0 are reserved for future use and should be masked out when checking the partition configuration register. Partition Configuration PC2 PC1PC0 PARTITIONING FOR DUAL WORK PARTITION0 PLANE3 PLANE2 PLANE1 PLANE0 PC2 PC1PC0 PARTITIONING FOR DUAL WORK PARTITION2 PARTITION1 PARTITION0 PLANE3 PLANE2 PLANE1 PLANE0 PLANE0 PLANE0 PLANE0 000 011 PARTITION1 PLANE3 PLANE2 PLANE1 PARTITION0 PLANE0 PARTITION2 PARTITION1 PARTITION0 PLANE3 PLANE2 001 110 PARTITION1 PLANE3 PLANE2 PARTITION0 PLANE1 PLANE0 PARTITION2 PARTITION1 PARTITION0 PLANE3 PLANE2 010 101 PARTITION1 PLANE3 PLANE2 PARTITION0 PLANE1 PLANE0 PARTITION3 PARTITION2 PARTITION1 PARTITION0 PLANE3 PLANE2 100 111 PLANE1 PLANE1 PLANE1 sharp 6.4 Memory Map for Flash Memory 6.4.1 Memory Map - F1 Selected Memory Area selected by BS="0" L R S1 8 3 0 18 BLOCK NUMBER ADDRESS RANGE Selected by BS=0 (Bank0) 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 1F8000H - 1FFFFFH 1F0000H - 1F7FFFH 1E8000H - 1EFFFFH 1E0000H - 1E7FFFH 1D8000H - 1DFFFFH 1D0000H - 1D7FFFH 1C8000H - 1CFFFFH 1C0000H - 1C7FFFH 1B8000H - 1BFFFFH 1B0000H - 1B7FFFH 1A8000H - 1AFFFFH 1A0000H - 1A7FFFH 198000H - 19FFFFH 190000H - 197FFFH 188000H - 18FFFFH 180000H - 187FFFH 178000H - 17FFFFH 170000H - 177FFFH 168000H - 16FFFFH 160000H - 167FFFH 158000H - 15FFFFH 150000H - 157FFFH 148000H - 14FFFFH 140000H - 147FFFH 138000H - 13FFFFH 130000H - 137FFFH 128000H - 12FFFFH 120000H - 127FFFH 118000H - 11FFFFH 110000H - 117FFFH 108000H - 10FFFFH 100000H - 107FFFH 0F8000H - 0FFFFFH 0F0000H - 0F7FFFH 0E8000H - 0EFFFFH 0E0000H - 0E7FFFH 0D8000H - 0DFFFFH 0D0000H - 0D7FFFH 0C8000H - 0CFFFFH 0C0000H - 0C7FFFH 0B8000H - 0BFFFFH 0B0000H - 0B7FFFH 0A8000H - 0AFFFFH 0A0000H - 0A7FFFH 098000H - 09FFFFH 090000H - 097FFFH 088000H - 08FFFFH 080000H - 087FFFH 078000H - 07FFFFH 070000H - 077FFFH 068000H - 06FFFFH 060000H - 067FFFH 058000H - 05FFFFH 050000H - 057FFFH 048000H - 04FFFFH 040000H - 047FFFH 038000H - 03FFFFH 030000H - 037FFFH 028000H - 02FFFFH 020000H - 027FFFH 018000H - 01FFFFH 010000H - 017FFFH 008000H - 00FFFFH 007000H - 007FFFH 006000H - 006FFFH 005000H - 005FFFH 004000H - 004FFFH 003000H - 003FFFH 002000H - 002FFFH 001000H - 001FFFH 000000H - 000FFFH BLOCK NUMBER 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD ADDRESS RANGE 3F8000H - 3FFFFFH 3F0000H - 3F7FFFH 3E8000H - 3EFFFFH 3E0000H - 3E7FFFH 3D8000H - 3DFFFFH 3D0000H - 3D7FFFH 3C8000H - 3CFFFFH 3C0000H - 3C7FFFH 3B8000H - 3BFFFFH 3B0000H - 3B7FFFH 3A8000H - 3AFFFFH 3A0000H - 3A7FFFH 398000H - 39FFFFH 390000H - 397FFFH 388000H - 38FFFFH 380000H - 387FFFH 378000H - 37FFFFH 370000H - 377FFFH 368000H - 36FFFFH 360000H - 367FFFH 358000H - 35FFFFH 350000H - 357FFFH 348000H - 34FFFFH 340000H - 347FFFH 338000H - 33FFFFH 330000H - 337FFFH 328000H - 32FFFFH 320000H - 327FFFH 318000H - 31FFFFH 310000H - 317FFFH 308000H - 30FFFFH 300000H - 307FFFH 2F8000H - 2FFFFFH 2F0000H - 2F7FFFH 2E8000H - 2EFFFFH 2E0000H - 2E7FFFH 2D8000H - 2DFFFFH 2D0000H - 2D7FFFH 2C8000H - 2CFFFFH 2C0000H - 2C7FFFH 2B8000H - 2BFFFFH 2B0000H - 2B7FFFH 2A8000H - 2AFFFFH 2A0000H - 2A7FFFH 298000H - 29FFFFH 290000H - 297FFFH 288000H - 28FFFFH 280000H - 287FFFH 278000H - 27FFFFH 270000H - 277FFFH 268000H - 26FFFFH 260000H - 267FFFH 258000H - 25FFFFH 250000H - 257FFFH 248000H - 24FFFFH 240000H - 247FFFH 238000H - 23FFFFH 230000H - 237FFFH 228000H - 22FFFFH 220000H - 227FFFH 218000H - 21FFFFH 210000H - 217FFFH 208000H - 20FFFFH 200000H - 207FFFH PLANE3 (UNIFORM PLANE) PLANE2 (UNIFORM PLANE) PLANE0 (PARAMETER PLANE) PLANE1 (UNIFORM PLANE) sharp Memory Area selected by BS="1" L R S1 8 3 0 19 BLOCK NUMBER ADDRESS RANGE 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 3FF000H - 3FFFFFH 3FE000H - 3FEFFFH 3FD000H - 3FDFFFH 3FC000H - 3FCFFFH 3FB000H - 3FBFFFH 3FA000H - 3FAFFFH 3F9000H - 3F9FFFH 3F8000H - 3F8FFFH 3F0000H - 3F7FFFH 3E8000H - 3EFFFFH 3E0000H - 3E7FFFH 3D8000H - 3DFFFFH 3D0000H - 3D7FFFH 3C8000H - 3CFFFFH 3C0000H - 3C7FFFH 3B8000H - 3BFFFFH 3B0000H - 3B7FFFH 3A8000H - 3AFFFFH 3A0000H - 3A7FFFH 398000H - 39FFFFH 390000H - 397FFFH 388000H - 38FFFFH 380000H - 387FFFH 378000H - 37FFFFH 370000H - 377FFFH 368000H - 36FFFFH 360000H - 367FFFH 358000H - 35FFFFH 350000H - 357FFFH 348000H - 34FFFFH 340000H - 347FFFH 338000H - 33FFFFH 330000H - 337FFFH 328000H - 32FFFFH 320000H - 327FFFH 318000H - 31FFFFH 310000H - 317FFFH 308000H - 30FFFFH 300000H - 307FFFH 2F8000H - 2FFFFFH 2F0000H - 2F7FFFH 2E8000H - 2EFFFFH 2E0000H - 2E7FFFH 2D8000H - 2DFFFFH 2D0000H - 2D7FFFH 2C8000H - 2CFFFFH 2C0000H - 2C7FFFH 2B8000H - 2BFFFFH 2B0000H - 2B7FFFH 2A8000H - 2AFFFFH 2A0000H - 2A7FFFH 298000H - 29FFFFH 290000H - 297FFFH 288000H - 28FFFFH 280000H - 287FFFH 278000H - 27FFFFH 270000H - 277FFFH 268000H - 26FFFFH 260000H - 267FFFH 258000H - 25FFFFH 250000H - 257FFFH 248000H - 24FFFFH 240000H - 247FFFH 238000H - 23FFFFH 230000H - 237FFFH 228000H - 22FFFFH 220000H - 227FFFH 218000H - 21FFFFH 210000H - 217FFFH 208000H - 20FFFFH 200000H - 207FFFH Selected by BS=1 (Bank1) BLOCK NUMBER ADDRESS RANGE 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 1F8000H - 1FFFFFH 1F0000H - 1F7FFFH 1E8000H - 1EFFFFH 1E0000H - 1E7FFFH 1D8000H - 1DFFFFH 1D0000H - 1D7FFFH 1C8000H - 1CFFFFH 1C0000H - 1C7FFFH 1B8000H - 1BFFFFH 1B0000H - 1B7FFFH 1A8000H - 1AFFFFH 1A0000H - 1A7FFFH 198000H - 19FFFFH 190000H - 197FFFH 188000H - 18FFFFH 180000H - 187FFFH 178000H - 17FFFFH 170000H - 177FFFH 168000H - 16FFFFH 160000H - 167FFFH 158000H - 15FFFFH 150000H - 157FFFH 148000H - 14FFFFH 140000H - 147FFFH 138000H - 13FFFFH 130000H - 137FFFH 128000H - 12FFFFH 120000H - 127FFFH 118000H - 11FFFFH 110000H - 117FFFH 108000H - 10FFFFH 100000H - 107FFFH 0F8000H - 0FFFFFH 0F0000H - 0F7FFFH 0E8000H - 0EFFFFH 0E0000H - 0E7FFFH 0D8000H - 0DFFFFH 0D0000H - 0D7FFFH 0C8000H - 0CFFFFH 0C0000H - 0C7FFFH 0B8000H - 0BFFFFH 0B0000H - 0B7FFFH 0A8000H - 0AFFFFH 0A0000H - 0A7FFFH 098000H - 09FFFFH 090000H - 097FFFH 088000H - 08FFFFH 080000H - 087FFFH 078000H - 07FFFFH 070000H - 077FFFH 068000H - 06FFFFH 060000H - 067FFFH 058000H - 05FFFFH 050000H - 057FFFH 048000H - 04FFFFH 040000H - 047FFFH 038000H - 03FFFFH 030000H - 037FFFH 028000H - 02FFFFH 020000H - 027FFFH 018000H - 01FFFFH 010000H - 017FFFH 008000H - 00FFFFH 000000H - 007FFFH PLANE3 (PARAMETER PLANE) PLANE2 (UNIFORM PLANE) PLANE0 (UNIFORM PLANE) PLANE1 (UNIFORM PLANE) sharp 6.4.2 Memory Map - F2 Selected Memory Area selected by BS="0" L R S1 8 3 0 20 BLOCK NUMBER ADDRESS RANGE Selected by BS=0 (Bank0) 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 1F8000H - 1FFFFFH 1F0000H - 1F7FFFH 1E8000H - 1EFFFFH 1E0000H - 1E7FFFH 1D8000H - 1DFFFFH 1D0000H - 1D7FFFH 1C8000H - 1CFFFFH 1C0000H - 1C7FFFH 1B8000H - 1BFFFFH 1B0000H - 1B7FFFH 1A8000H - 1AFFFFH 1A0000H - 1A7FFFH 198000H - 19FFFFH 190000H - 197FFFH 188000H - 18FFFFH 180000H - 187FFFH 178000H - 17FFFFH 170000H - 177FFFH 168000H - 16FFFFH 160000H - 167FFFH 158000H - 15FFFFH 150000H - 157FFFH 148000H - 14FFFFH 140000H - 147FFFH 138000H - 13FFFFH 130000H - 137FFFH 128000H - 12FFFFH 120000H - 127FFFH 118000H - 11FFFFH 110000H - 117FFFH 108000H - 10FFFFH 100000H - 107FFFH 0F8000H - 0FFFFFH 0F0000H - 0F7FFFH 0E8000H - 0EFFFFH 0E0000H - 0E7FFFH 0D8000H - 0DFFFFH 0D0000H - 0D7FFFH 0C8000H - 0CFFFFH 0C0000H - 0C7FFFH 0B8000H - 0BFFFFH 0B0000H - 0B7FFFH 0A8000H - 0AFFFFH 0A0000H - 0A7FFFH 098000H - 09FFFFH 090000H - 097FFFH 088000H - 08FFFFH 080000H - 087FFFH 078000H - 07FFFFH 070000H - 077FFFH 068000H - 06FFFFH 060000H - 067FFFH 058000H - 05FFFFH 050000H - 057FFFH 048000H - 04FFFFH 040000H - 047FFFH 038000H - 03FFFFH 030000H - 037FFFH 028000H - 02FFFFH 020000H - 027FFFH 018000H - 01FFFFH 010000H - 017FFFH 008000H - 00FFFFH 007000H - 007FFFH 006000H - 006FFFH 005000H - 005FFFH 004000H - 004FFFH 003000H - 003FFFH 002000H - 002FFFH 001000H - 001FFFH 000000H - 000FFFH BLOCK NUMBER 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD ADDRESS RANGE 3F8000H - 3FFFFFH 3F0000H - 3F7FFFH 3E8000H - 3EFFFFH 3E0000H - 3E7FFFH 3D8000H - 3DFFFFH 3D0000H - 3D7FFFH 3C8000H - 3CFFFFH 3C0000H - 3C7FFFH 3B8000H - 3BFFFFH 3B0000H - 3B7FFFH 3A8000H - 3AFFFFH 3A0000H - 3A7FFFH 398000H - 39FFFFH 390000H - 397FFFH 388000H - 38FFFFH 380000H - 387FFFH 378000H - 37FFFFH 370000H - 377FFFH 368000H - 36FFFFH 360000H - 367FFFH 358000H - 35FFFFH 350000H - 357FFFH 348000H - 34FFFFH 340000H - 347FFFH 338000H - 33FFFFH 330000H - 337FFFH 328000H - 32FFFFH 320000H - 327FFFH 318000H - 31FFFFH 310000H - 317FFFH 308000H - 30FFFFH 300000H - 307FFFH 2F8000H - 2FFFFFH 2F0000H - 2F7FFFH 2E8000H - 2EFFFFH 2E0000H - 2E7FFFH 2D8000H - 2DFFFFH 2D0000H - 2D7FFFH 2C8000H - 2CFFFFH 2C0000H - 2C7FFFH 2B8000H - 2BFFFFH 2B0000H - 2B7FFFH 2A8000H - 2AFFFFH 2A0000H - 2A7FFFH 298000H - 29FFFFH 290000H - 297FFFH 288000H - 28FFFFH 280000H - 287FFFH 278000H - 27FFFFH 270000H - 277FFFH 268000H - 26FFFFH 260000H - 267FFFH 258000H - 25FFFFH 250000H - 257FFFH 248000H - 24FFFFH 240000H - 247FFFH 238000H - 23FFFFH 230000H - 237FFFH 228000H - 22FFFFH 220000H - 227FFFH 218000H - 21FFFFH 210000H - 217FFFH 208000H - 20FFFFH 200000H - 207FFFH PLANE3 (UNIFORM PLANE) PLANE2 (UNIFORM PLANE) PLANE0 (PARAMETER PLANE) PLANE1 (UNIFORM PLANE) sharp Memory Area selected by BS="1" L R S1 8 3 0 21 BLOCK NUMBER ADDRESS RANGE 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 3FF000H - 3FFFFFH 3FE000H - 3FEFFFH 3FD000H - 3FDFFFH 3FC000H - 3FCFFFH 3FB000H - 3FBFFFH 3FA000H - 3FAFFFH 3F9000H - 3F9FFFH 3F8000H - 3F8FFFH 3F0000H - 3F7FFFH 3E8000H - 3EFFFFH 3E0000H - 3E7FFFH 3D8000H - 3DFFFFH 3D0000H - 3D7FFFH 3C8000H - 3CFFFFH 3C0000H - 3C7FFFH 3B8000H - 3BFFFFH 3B0000H - 3B7FFFH 3A8000H - 3AFFFFH 3A0000H - 3A7FFFH 398000H - 39FFFFH 390000H - 397FFFH 388000H - 38FFFFH 380000H - 387FFFH 378000H - 37FFFFH 370000H - 377FFFH 368000H - 36FFFFH 360000H - 367FFFH 358000H - 35FFFFH 350000H - 357FFFH 348000H - 34FFFFH 340000H - 347FFFH 338000H - 33FFFFH 330000H - 337FFFH 328000H - 32FFFFH 320000H - 327FFFH 318000H - 31FFFFH 310000H - 317FFFH 308000H - 30FFFFH 300000H - 307FFFH 2F8000H - 2FFFFFH 2F0000H - 2F7FFFH 2E8000H - 2EFFFFH 2E0000H - 2E7FFFH 2D8000H - 2DFFFFH 2D0000H - 2D7FFFH 2C8000H - 2CFFFFH 2C0000H - 2C7FFFH 2B8000H - 2BFFFFH 2B0000H - 2B7FFFH 2A8000H - 2AFFFFH 2A0000H - 2A7FFFH 298000H - 29FFFFH 290000H - 297FFFH 288000H - 28FFFFH 280000H - 287FFFH 278000H - 27FFFFH 270000H - 277FFFH 268000H - 26FFFFH 260000H - 267FFFH 258000H - 25FFFFH 250000H - 257FFFH 248000H - 24FFFFH 240000H - 247FFFH 238000H - 23FFFFH 230000H - 237FFFH 228000H - 22FFFFH 220000H - 227FFFH 218000H - 21FFFFH 210000H - 217FFFH 208000H - 20FFFFH 200000H - 207FFFH Selected by BS=1 (Bank1) BLOCK NUMBER ADDRESS RANGE 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 1F8000H - 1FFFFFH 1F0000H - 1F7FFFH 1E8000H - 1EFFFFH 1E0000H - 1E7FFFH 1D8000H - 1DFFFFH 1D0000H - 1D7FFFH 1C8000H - 1CFFFFH 1C0000H - 1C7FFFH 1B8000H - 1BFFFFH 1B0000H - 1B7FFFH 1A8000H - 1AFFFFH 1A0000H - 1A7FFFH 198000H - 19FFFFH 190000H - 197FFFH 188000H - 18FFFFH 180000H - 187FFFH 178000H - 17FFFFH 170000H - 177FFFH 168000H - 16FFFFH 160000H - 167FFFH 158000H - 15FFFFH 150000H - 157FFFH 148000H - 14FFFFH 140000H - 147FFFH 138000H - 13FFFFH 130000H - 137FFFH 128000H - 12FFFFH 120000H - 127FFFH 118000H - 11FFFFH 110000H - 117FFFH 108000H - 10FFFFH 100000H - 107FFFH 0F8000H - 0FFFFFH 0F0000H - 0F7FFFH 0E8000H - 0EFFFFH 0E0000H - 0E7FFFH 0D8000H - 0DFFFFH 0D0000H - 0D7FFFH 0C8000H - 0CFFFFH 0C0000H - 0C7FFFH 0B8000H - 0BFFFFH 0B0000H - 0B7FFFH 0A8000H - 0AFFFFH 0A0000H - 0A7FFFH 098000H - 09FFFFH 090000H - 097FFFH 088000H - 08FFFFH 080000H - 087FFFH 078000H - 07FFFFH 070000H - 077FFFH 068000H - 06FFFFH 060000H - 067FFFH 058000H - 05FFFFH 050000H - 057FFFH 048000H - 04FFFFH 040000H - 047FFFH 038000H - 03FFFFH 030000H - 037FFFH 028000H - 02FFFFH 020000H - 027FFFH 018000H - 01FFFFH 010000H - 017FFFH 008000H - 00FFFFH 000000H - 007FFFH PLANE3 (PARAMETER PLANE) PLANE2 (UNIFORM PLANE) PLANE0 (UNIFORM PLANE) PLANE1 (UNIFORM PLANE) sharp L R S1 8 3 0 22 6.5 DC Electrical Characteristics for Flash Memory DC Electrical Characteristics (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol CIN CIO ILI ILO ICCS Parameter Input Capacitance I/O Capacitance Input Leakage Current Output Leakage Current VCC Standby Current 1, 9 8 Notes 4 4 Min. Typ. Max. 7 10 1 1 40 Unit pF pF Test Conditions VIN = 0V, f = 1MHz, TA = 25C VI/O = 0V, f = 1MHz, TA = 25C A VIN = VCC or GND A VOUT = VCC or GND VCC = VCC Max., A F-CE = F-RST = VCC 0.2V, WP/ACC = VCC or GND VCC = VCC Max., A F-CE = GND 0.2V, WP/ACC = VCC or GND A F-RST = GND 0.2V IOUT (F-RY/BY) = 0mA ICCAS VCC Automatic Power Savings Current 1, 3, 6 8 40 ICCD VCC Reset Power-Down Current Average VCC Read Current Normal Mode Average VCC Read Current Page Mode 8 Word Read 1 8 40 1, 6, 8 15 30 mA V = V Max., CC CC F-CE = VIL, OE = VIH, f = 5MHz IOUT = 0mA ICCR 1, 6, 8 1, 4, 7, 8 1, 4, 7, 8 1, 4, 7, 8 1, 4, 7, 8 1, 2, 8 1, 5, 8 10 40 20 20 8 20 4 4 20 4 10 4 50 4 50 15 120 40 60 20 400 10 10 60 10 30 10 400 10 400 mA ICCW VCC (Page Buffer) Program Current mA WP/ACC = VACCH1 mA WP/ACC = VACCH2 mA WP/ACC = VACCH1 mA WP/ACC = VACCH2 A F-CE = VIH A WP/ACC VCC ICCE ICCWS ICCES IACCS IACCR IACCW VCC Block Erase, Bank Erase Current VCC (Page Buffer) Program or Block Erase Suspend Current WP/ACC Standby or Read Current WP/ACC Current (Page Buffer) Program 1,4,5,7,8 1,4,5,7,8 1,4,5,7,8 1,4,5,7,8 1, 5, 8 1, 5, 8 1, 5, 8 1, 5, 8 A WP/ACC = VACCH1 mA WP/ACC = VACCH2 A WP/ACC = VACCH1 mA WP/ACC = VACCH2 A WP/ACC = VACCH1 A WP/ACC = VACCH2 A WP/ACC = VACCH1 A WP/ACC = VACCH2 IACCE WP/ACC Block Erase, Bank Erase Current WP/ACC (Page Buffer) Program Suspend Current IACCWS IACCES WP/ACC Block Erase Suspend Current sharp L R S1 8 3 0 23 DC Electrical Characteristics (Continue) (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol VIL VIH VOL VOH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Notes Min. 4 4 4, 9 4 5 5 VCC -0.2 -0.4 11.7 1.5 3 12 3.1 12.3 -0.4 2.4 Typ. Max. 0.4 VCC +0.4 0.2 Unit V V V V V V V VCC = VCC Min, IOL = 100 A IOH = 100 A Test Conditions VACCH1 WP/ACC during Block Erase, Bank Erase, (Page Buffer) Program Operations VACCH2 WP/ACC during Block Erase, Bank Erase, (Page Buffer) Program Operations VLKO Notes: VCC Lockout Voltage 1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC = 3.0V and TA = +25 C unless VCC is specified. 2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block erase suspend mode, the device's current draw is the sum of ICCES and ICCR or ICCW. If read is executed while in (page buffer) program suspend mode, the device's current draw is the sum of ICCWS and ICCR. 3. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when addresses are changed. 4. Sampled, not 100% tested. 5. Applying 12V0.3V to WP/ACC provides fast erasing or fast programming mode. In this mode, WP/ACC is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and layout considerations given to the VCC power bus. Applying 12V0.3V to WP/ACC during erase/program can only be done for a maximum of 1,000 cycles on each block. WP/ACC may be connected to 12V0.3V for a total of 80 hours maximum. 6. Never hold F1-CE low and F2-CE low at the same timing. 7. F1 and F2 should not be operated at the same timing to Block erase, bank erase, (page buffer) program. 8. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane. 9. Includes F-RY/BY sharp 6.6 AC Electrical Characteristics for Flash Memory 6.6.1 AC Test Conditions (1) Input Pulse Level Input Rise and Fall Time Input and Output Timing Ref. level Output Load Notes: 1. The capacitance in a chip is not included. 6.6.2 Read Cycle L R S1 8 3 0 24 0 V to 2.7 V 5 ns 1/2 VCC 1TTL +CL (50pF) (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol tAVAV tAVQV tBLQV tELQV tAPA tGLQV tPHQV tEHQZ, tGHQZ tELQX tGLQX tOH tAVEL, tAVGL tELAX, tGLAX tEHEL, tGHGL tAVBV tBVAX tBVBV Notes: 1. Sampled, not 100% tested. 2. OE may be delayed up to tELQV tGLQV after the falling edge of F-CE without impact to tELQV. 3. Address setup time (tAVEL, tAVGL) is defined from the falling edge of F-CE or OE (whichever goes low last). 4. Address hold time (tELAX, tGLAX) is defined from the falling edge of F-CE or OE (whichever goes low last). 5. Specifications tAVEL, tAVGL, tELAX, tGLAX and tEHEL, tGHGL for read operations apply to only status register read operations. 6. Specifications tAVBV, tBVAX and tBVBV for read operations apply to only status register read operations. Read Cycle Time Address to Output Delay BS to Output Delay F-CE to Output Delay Page Address Access Time OE to Output Delay F-RST High to Output Delay F-CE or OE to Output in High-Z, Whichever Occurs First F-CE to Output in Low-Z OE to Output in Low-Z Output Hold from First Occurring Address, F-CE or OE Change Address Setup to F-CE and OE Going Low for Reading Status Register Address Hold from F-CE and OE Going Low for Reading Status Register F-CE and OE Pulse Width High for Reading Status Register Address Setup to BS (Bank Select) for Reading Status Register Address Hold from BS (Bank Select) for Reading Status Register BS Pulse Width High for Reading Status Register 1 1 1 1 3,5 4,5 5 6 6 6 0 0 0 10 30 20 10 30 20 2 2 Parameter Notes Min. 70 70 70 70 35 20 150 20 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns sharp 6.6.3 Write Cycle (WE / F-CE Controlled) (1, 2) L R S1 8 3 0 25 (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol tAVAV tPHWL (tPHEL) tBLWL, tWLBL tELWL (tWLEL) Write Cycle Time F-RST High Recovery to WE (F-CE) Going Low BS Setup to WE Going Low F-CE (WE) Setup to WE (F-CE) Going Low 4 4 8 8 3 Parameter Notes Min. 70 150 0 0 50 40 50 50 0 0 0 0 0 5 3 20 200 30 3, 6 3, 7 3 0 tAVQV+50 100 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tWLWH (tELEH) WE (F-CE) Pulse Width tDVWH (tDVEH) Data Setup to WE (F-CE) Going High tAVWH (tAVEH) Address Setup to WE (F-CE) Going High tBVWH (tBVEH) tWHBH, tWHBL BS Setup to WE (F-CE) Going High BS Hold from WE High tWHEH (tEHWH) F-CE (WE) Hold from WE (F-CE) High tWHDX (tEHDX) Data Hold from WE (F-CE) High tWHAX (tEHAX) Address Hold from WE (F-CE) High tWHBX (tEHBX) BS Hold from WE (F-CE) Going High tWHWL (tEHEL) WE (F-CE) Pulse Width High tVVWH (tVVEH) WP/ACC Setup to WE (F-CE) Going High tWHGL (tEHGL) Write Recovery before Read tQVVL tWHR0 (tEHR0) WP/ACC Hold from Valid SRD, F-RY/BY High-Z WE (F-CE) High to SR.7 Going "0" tWHRL (tEHRL) WE (F-CE) High to F-RY/BY Going Low Notes: 1. The timing characteristics for reading the status register during block erase, bank erase, (page buffer) program operations are the same as during read-only operations. See the AC Characteristics for read cycle. 2. A write operation can be initiated and terminated with either F-CE or WE. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from the falling or rising edge of BS or the falling edge of F-CE or WE (whichever occurs last) to the rising or falling edge of BS or the rising edge of F-CE or WE (whichever occurs first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH=tBLBH=tWLBH=tBLWH. 5. Write pulse width high (tWPH) is defined from the rising edge of F-CE or WE (whichever goes high first) to the falling edge of F-CE or WE (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. 6. WP/ACC should be held at WP/ACC=VACCH1/2 until determination of block erase, bank erase, (page buffer) program success (SR.1/3/4/5=0). 7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes command=tAVQV+100ns. 8. See 6.2.1 Command Definitions for valid address and data for block erase, bank erase, (page buffer) program or lock bit configuration. sharp L R S1 8 3 0 26 6.6.4 Block Erase, Bank Erase, (Page Buffer) Program Performance (3) (TA = -30C to +85C, VCC = 2.7V to 3.1V) Page Buffer Command Notes is Used or not Used 2 2 2 2 2 2 2 2 2 4 4 Not Used Used Not Used Used Not Used Used WP/ACC=VACCH1 Min. Typ.(1) Max.(2) 0.05 0.03 0.38 0.24 11 7 0.3 0.6 80 5 5 0.3 0.12 2.4 1 200 100 4 5 700 10 20 WP/ACC=VACCH2 Min. Typ.(1) Max.(2) 0.04 0.02 0.31 0.17 9 5 0.2 0.5 65 5 5 0.12 0.06 1 0.5 185 90 4 5 700 10 20 Unit s s s s s s s s s s s Symbol Parameter tWPB tWMB 4K-Word Parameter Block Program Time 32K-Word Main Block Program Time tWHQV1/ Word Program Time tEHQV1 tWHQV2/ 4K-Word Parameter Block Erase tEHQV2 Time tWHQV3/ 32K-Word Main Block Erase Time tEHQV3 Bank Erase Time tWHRH1/ (Page Buffer) Program Suspend Latency tEHRH1 Time to Read tWHRH2/ Block Erase Suspend Latency Time tEHRH2 to Read tERES Notes: Latency Time from Block Erase Resume Command to Block Erase Suspend Command 5 - 500 500 s 1. Typical values measured at VCC =3.0V, WP/ACC =3.0V or 12V, and TA=+25 C. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. 4. A latency time is required from writing suspend command (WE or F-CE going high) until SR.7 going "1" or F-RY/BY going High-Z. 5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished. sharp 6.6.5 Flash Memory AC Characteristics Timing Chart L R S1 8 3 0 27 AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes or Query Code A21-0 (A) VIH VIL VALID ADDRESS tAVAV tAVQV tBVBV VIH VIL tAVBV tBVAX tEHEL VIH VIL tGHQZ VALID INPUT tBLQV, tBHQV BS (B) F-CE (E) tAVEL tELAX tAVGL tGHGL tGLAX OE (G) VIH VIL tELQV WE (W) VIH VIL tGLQV tGLQX tELQX tOH tOH DQ15-0 (D/Q) VOH VOL High-Z VALID OUTPUT tPHQV VIH F-RST (P) VIL sharp L R S1 8 3 0 28 AC Waveform for Asynchronous 4-Word Page Mode Read Operations from Main Blocks or Parameter Blocks A21-3 (A) VIH VIL VALID ADDRESS tAVAV tAVQV A2-0 (A) VIH VIL VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS BS (B) VIH VIL tBLQV VALID INPUT VIH F-CE (E) VIL tELQV tEHQZ tGHQZ VIH OE (G) VIL VIH WE (W) VIL tGLQX tELQX VOH VOL tPHQV tGLQV tAPA tOH DQ15-0 (D/Q) High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VIH F-RST (P) VIL sharp L R S1 8 3 0 29 AC Waveform for Asynchronous 8-Word Page Mode Read Operations from Main Blocks or Parameter Blocks A21-3 (A) VIH VIL tAVQV VALID ADDRESS tAVAV A2-0 (A) VIH VIL VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID VALID VALID ADDRESS ADDRESS ADDRESS VALID ADDRESS BS (B) VIH VIL VALID INPUT tBLQV IH F-CE (E) V V IL tELQV tEHQZ tGHQZ OE (G) VIH V IL WE (W) VIH V IL tGLQX tELQX tGLQV tAPA VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID VALID OUTPUT OUTPUT VALID OUTPUT VALID OUTPUT tOH VALID OUTPUT DQ15-0 (D/Q) VOH VOL High Z tPHQV F-RST (P) VIL VIH sharp L R S1 8 3 0 30 AC Waveform for Write Operations (WE / F-CE) 1 (WP/ACC : VACCH1 Selected) NOTE 1 A21-0 (A) VIH VIL NOTE 2 VALID ADDRESS tAVAV NOTE 3 VALID ADDRESS tAVWH (tAVEH) NOTE 4 VALID ADDRESS NOTE 5 tWHAX (tEHAX) VIH VIL tBLWL ,tWLBL tWHBH ,tWHBL BS (B) VIH F-CE (E) NOTES 5, 6 tELWL (tWLEL) tWHEH (tEHWH) tWHGL (tEHGL) VIL VIH NOTES 5, 6 OE (G) VIL tPHWL (tPHEL) tWHWL (tEHEL) WE (W) VIH VIL tWLWH (tELEH ) tWHDX (tEHDX) tDVWH (tDVEH) tWHQV1,2,3 (tEHQV1,2,3) DQ15-0 (D/Q) VIH VIL DATA IN DATA IN VALID SRD tWHRL (tEHRL) High-Z (tWHR0 (tEHR0)) F-RY/BY (R) (SR.7) (1) VOL (0) F-RST (P) VIH VIL Notes: 1. VCC power-up and standby. 2. Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operation, OE and F-CE must be driven active, and WE de-asserted. sharp L R S1 8 3 0 31 AC Waveform for Write Operations (WE / F-CE) 2 (WP/ACC : VACCH2 Selected) NOTE 1 A21-0 (A) VIH VIL NOTE 2 VALID ADDRESS tAVAV NOTE 3 VALID ADDRESS tAVWH (tAVEH) NOTE 4 VALID ADDRESS NOTE 5 tWHAX (tEHAX) VIH VIL tBLWL ,tWLBL tWHBH ,tWHBL BS (B) VIH F-CE (E) VIL tELWL (tWLEL) tWHEH (tEHWH) tWHGL (tEHGL) VIH NOTES 5, 6 OE (G) VIL tPHWL (tPHEL) tWHWL (tEHEL) WE (W) VIH VIL tWLWH (tELEH ) tWHDX (tEHDX) tDVWH (tDVEH) tWHQV1,2,3 (tEHQV1,2,3) DQ15-0 (D/Q) VIH VIL DATA IN DATA IN VALID SRD tWHRL (tEHRL) High-Z (tWHR0 (tEHR0)) F-RY/BY (R) (SR.7) (1) VOL (0) F-RST (P) VIH VIL tVVWH (tVVEH) tQVVL WP/ACC (V) VACCH2 VIL Notes: 1. VCC power-up and standby. 2. Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operation, OE and F-CE must be driven active, and WE de-asserted. sharp 6.6.6 Reset Operations L R S1 8 3 0 32 (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol tPLPH tPLRH tVPH tVHQV Notes: 1. A reset time, tPHQV, is required from the later of SR.7 (F-RY/BY) going "1" (High-Z) or F-RST going high until outputs are valid. See the AC Characteristics - read cycle for tPHQV. 2. tPLPH is <100ns the device may still reset but this is not guaranteed. 3. Sampled, not 100% tested. 4. If F-RST asserted while a block erase, bank erase or (page buffer) program operation is not executing, the reset will complete within 100ns. 5. When the device power-up, holding F-RST low minimum 100ns is required after VCC has been in predefined range and also has been in stable there. AC Waveform for Reset Operation Parameter F-RST Low to Reset during Read (F-RST should be low during power-up.) F-RST Low to Reset during Erase or Program VCC = 2.7V to F-RST High VCC = 2.7V to Output Delay Notes 1, 2, 3 1, 3, 4 1, 3, 5 3 100 1 Min. 100 22 Max. Unit ns s ns ms F-RST (P) VIH VIL High-Z tPHQV tPLPH (A) Reset during Read Array Mode tPLRH tPLPH High-Z ABORT SR.7=1 COMPLETE VALID OUTPUT DQ15-0 (D/Q) VOH VOL VIH VIL DQ15-0 (D/Q) VOH VOL F-RST (P) VCC 2.7V GND tPHQV (B) Reset during Erase or Program Mode tVHQV tVPH tPHQV VALID OUTPUT F-RST (P) VIH VIL High-Z DQ15-0 (D/Q) VOH VOL (C) F-RST rising timing VALID OUTPUT sharp 7. Smartcombo RAM 7.1 Truth Table 7.1.1 Bus Operation (1) L R S1 8 3 0 33 Smartcombo RAM Read Output Disable Write Notes SC-CE1 SC-CE2 OE L WE H H L LB (3) X (3) X UB DQ0 to Q15 (3) L H H H H X High - Z (3) X H X High - Z Standby Sleep Notes: 2 X X L X X H X 1. L = VIL, H = VIH, X = H or L, High-Z = High impedance. Refer to the DC Characteristics. 2. SC-CE2 pin must be fixed to high level except sleep mode. 3. LB, UB Control Mode LB L L H UB L H L DQ0 to DQ7 DOUT/DIN DOUT/DIN High - Z DQ8 to DQ15 DOUT/DIN High - Z DOUT/DIN sharp 7.2 DC Electrical Characteristics for Smartcombo RAM L R S1 8 3 0 34 DC Electrical Characteristics (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol CIN CIO ILI ILO ISB ISLP ICC1 VIL VIH VOL VOH Notes: 1. Sampled, not 100% tested. 2. Memory cell data is held. (SC-CE2 = "VIH") 3. Memory cell data is not held. (SC-CE2 = "VIL") Parameter Input Capacitance I/O Capacitance Input Leakage Current Output Leakage Current VCC Standby Current VCC Sleep Mode Current VCC Operation Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 1 1 1 1 0.8VCC -0.4 2.4 2 3 Notes 1 1 Min. Typ. Max. 8 10 1 1 180 100 50 0.4 VCC +0.4 0.2VCC Unit pF pF A A A A mA V V V V IOL = 0.5mA IOH = -0.5mA VIN = 0V VI/O = 0V VIN = VCC or GND VOUT = VCC or GND SC-CE1 SC-CE1 VCC - 0.2V, SC-CE2 VCC - 0.2V, SC-CE2 0.2V 0.2V Test Conditions tCYCLE = Min., II/O = 0mA, SC-CE1 = VIL sharp 7.3 AC Electrical Characteristic for Smartcombo RAM 7.3.1 AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Ref. Level Output Load Notes: 1. Including scope and socket capacitance. L R S1 8 3 0 35 0.2VCC to 0.8VCC 5 ns 1/2 VCC 1TTL +CL (50pF) (1, 2) 2. AC characteristics directed with the note should be measured with the output load shown in below. DQ (Output) Zo = 50 50 1/2 VCC CL sharp 7.3.2 Read Cycle L R S1 8 3 0 36 (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol tRC tAA tACE tOE tBE tPAA tOH tPRC tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASO tOHAH tCHAH tBHAH tCLOL tOLCH tCP tBP tOP Notes: 1. tCLOL and tOP (Max.) are applied while SC-CE1 is being hold at low level. 2. tBHAH is specified after both LB and UB are High. Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Byte Enable Access Time Page Access Time Output Hold from Address Change Page Read Cycle Time SC-CE1 Low to Output Active OE Low to Output Active UB or LB Low to Output Active SC-CE1 High to Output in High-Z OE High to Output in High-Z UB or LB High to Output in High-Z Address Setup to OE Low OE High Level to Address Hold SC-CE1 High Level to Address Hold LB, UB High Level to Address Hold SC-CE1 Low Level to OE Low Level OE Low Level to SC-CE1 High Level SC-CE1 High Level Pulse Width LB, UB High Level Pulse Width OE High Level Pulse Width 1 2 1 0 -5 0 0 0 45 10 10 2 10,000 10,000 5 18 10 5 5 25 25 25 Parameter Notes Min. 70 70 70 45 70 18 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns sharp 7.3.3 Write Cycle L R S1 8 3 0 37 (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol tWC tCW tAW tBW tWP tWR tCP tBP tWHP tWHZ tOW tAS tDW tDH tOHAH tCHAH tBHAH tOES tOEH Notes: 1. tOES and tOEH (Max.) are applied while SC-CE1 is being hold at low level. 2. tBHAH is specified after both LB and UB are High. Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select Time Write Pulse Width Write Recovery Time SC-CE1 High Level Pulse Width LB, UB High Level Pulse Width WE High Pulse Width WE Low to Output in High-Z WE High to Output Active Address Setup Time Input Data Setup Time Input Data Hold Time OE High Level to Address Hold SC-CE1 High Level to Address Hold LB, UB High Level to Address Hold OE High Level to WE Set WE High Level to OE Set 2 1 1 15 0 30 0 -5 0 0 0 10 10,000 10,000 Parameter Notes Min. 70 55 55 55 50 0 10 10 10 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns sharp 7.3.4 Initialization L R S1 8 3 0 38 (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol Parameter Notes Min. 50 10 300 Max. Unit s ns s tVHMH Power Application to SC-CE2 Low Level Hold tCHMH SC-CE1 High Level to SC-CE2 High Level tMHCL Following Power Application SC-CE2 High Level Hold to SC-CE1 Low Level 7.3.5 Sleep Mode Entry / Exit (TA = -30C to +85C, VCC = 2.7V to 3.1V) Symbol tCHML tMHCL Parameter Sleep Mode Entry SC-CE1 High Level to SC-CE2 Low Level Sleep Mode Exit to Normal Operation SC-CE2 High Level to SC-CE1 Low Level Notes Min. 0 300 Max. Unit ns s sharp 7.4 Initialization L R S1 8 3 0 39 Initialize the power application using the following sequence to stabilize internal circuits. (1) Following power application, make SC-CE2 high level after fixing SC-CE2 to low level for the period of tVHMH. Make SC-CE1 high level before making SC-CE2 high level. (2) SC-CE1 and SC-CE2 are fixed to high level for the period of tMHCL. Normal operation is possible after the completion of initialization. Initialization VIH Normal Operation SC-CE1 VIL tCHMH tVHMH tMHCL VIH SC-CE2 VIL VCC VCC (Min.) Notes: 1. Make SC-CE2 low level when starting the power supply. 2. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (VCC Min.). sharp Standby Mode State Machine L R S1 8 3 0 40 Power On Initialization Initial State SC-CE1 = VIL Active SC-CE1 = VIH, SC-CE2 = VIH SC-CE1 = VIL, SC-CE2 = VIH SC-CE2 = VIH SC-CE1 = VIH or VIL, SC-CE2 = VIL Standby Mode SC-CE1 = VIH or VIL, SC-CE2 = VIL Sleep mode sharp 7.5 Page Read Operation 7.5.1 Features of Page Read Operation (2) Features Page Length Page Read-corresponding Addresses Page Read Start Address Page Direction Interrupt during page read operation Notes: 1 Notes L R S1 8 3 0 41 8 Words Mode 8 words A2, A1, A0 Don't care Don't care Enabled 1. An interrupt is output when SC-CE1 = High or in case A3 or a higher address changes. 2. Page Length: 8 words is supported as the page lengths. Page-Corresponding Addresses: The page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and A0 during page read operation. Page Start Address: Since random page read is supported, any address (A2, A1, A0) can be used as the page read start address. Page Direction: Since random page read is possible, there is not restriction on the page direction. Interrupt during Page Read Operation: When generating an interrupt during page read, either make SC-CE1 high level or change A3 and higher addresses. When page read is not used: Since random page read is supported, even when not using page read, random access is possible as usual. sharp 7.6 Mode Register Settings L R S1 8 3 0 42 The sleep mode can be set using the mode register. Since the initial value of the mode register at power application is undefined, be sure to set the mode register after initialization at power application. However, since sleep mode is not entered unless SC-CE2 = Low when sleep mode is not used, it is not necessary to set the mode register. Moreover, when using page read without using sleep mode, it is not necessary to set the mode register. 7.6.1 Mode Register Setting Method The mode register setting mode can be entered by successively writing two specific data after two continuous reads of the highest address (1FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two write cycles). Commands are written to the command register. The command register is used to latch the addresses and data required for executing commands, and it does not have an exclusive memory area. For the timing chart and flow chart, refer to Mode Register Setting Timing Chart (P.55), Mode Register Setting Flow Chart (P.56). Following table shows the commands and command sequences. Command Sequence Command Sequence 1st Bus Cycle (Read Cycle) Address Sleep Mode 4th Bus Cycle (Write cycle) DQ Mode Register Setting 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 PL 1 1 0 1 1FFFFFH Data 2nd Bus Cycle (Read Cycle) Address 1FFFFFH Data 3rd Bus Cycle (Write Cycle) Address 1FFFFFH Data 00H 4th Bus Cycle (Write Cycle) Address 1FFFFFH Data 07H Page Length 1 8 words sharp 7.6.2 Cautions for Setting Mode Register L R S1 8 3 0 43 Since, for the mode register setting, the internal counter status is judged by toggling SC-CE1 and S-OE, toggle SC-CE1 at every cycle during entry (read cycle twice, write cycle twice), and toggle S-OE like SC-CE1 at the first and second read cycles. If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the mode register are not performed correctly. When the highest address (1FFFFFH) is read consecutively three or more times, the mode register setting entries are cancelled. Once the sleep mode has been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. For the timing chart and flow chart, refer to Mode Register Setting Timing Chart (P.55), Mode Register Setting Flow Chart (P.56). sharp L R S1 8 3 0 44 7.7 Smartcombo RAM AC Characteristics Timing Chart Read Cycle Timing Chart 1 (SC-CE1 Controlled) tRC tRC Address VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High - Z ADDRESS STABLE tACE tCHAH tCP ADDRESS STABLE tACE tCHAH tCP SC-CE1 tCLZ tCHZ tCLZ tCHZ OE UB LB DOUT VALID OUTPUT VALID OUTPUT High - Z Note: 1. In read cycle, SC-CE2 and WE should be fixed to high level. sharp Read Cycle Timing Chart 2 (OE Controlled) L R S1 8 3 0 45 tRC tRC Address VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High - Z tASO ADDRESS STABLE tAA tOE tBHAH tOHAH tOP tASO ADDRESS STABLE tAA tOE tBHAH tOHAH tOP tASO SC-CE1 OE UB LB DOUT tOLZ tOHZ VALID OUTPUT tOLZ tOHZ VALID OUTPUT High - Z Note: 1. In read cycle, SC-CE2 and WE should be fixed to high level. sharp Read Cycle Timing Chart 3 (SC-CE1 / OE Controlled) L R S1 8 3 0 46 tRC tRC tOHAH tAA Address VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High - Z tCLOL ADDRESS STABLE tACE ADDRESS STABLE tBHAH tOHZ tASO tCHAH tBHAH tCHZ SC-CE1 tCLZ tOE tOE tOHAH tOLZ tOHZ OE UB LB DOUT tOLZ VALID OUTPUT VALID OUTPUT High - Z Note: 1. In read cycle, SC-CE2 and WE should be fixed to high level. sharp Read Cycle Timing Chart 4 (Address Controlled) L R S1 8 3 0 47 tRC tRC VIH Address VIL VIH SC-CE1 VIL VIH OE VIL VIH VIL tOH ADDRESS STABLE tAA ADDRESS STABLE tAA UB LB tOH VALID OUTPUT VALID OUTPUT tOH VOH DOUT VOL Notes: 1. In read cycle, SC-CE2 and WE should be fixed to high level. 2. When read cycle time is less than tRC (Min.), the address access time (tAA) is not guaranteed. sharp Read Cycle Timing Chart 5 (LB / UB Controlled) L R S1 8 3 0 48 tRC tRC Address VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High - Z ADDRESS STABLE ADDRESS STABLE SC-CE1 OE UB LB DOUT tBHAH tBE tBLZ tBP tBE tBLZ tBHAH tBP tBHZ VALID OUTPUT tBHZ VALID OUTPUT Note: 1. In read cycle, SC-CE2 and WE should be fixed to high level. sharp 8 Word Page Read Cycle Timing Chart L R S1 8 3 0 49 Address (A3 to A20) VIH VIL tRC tPRC tPRC ADDRESS STABLE tPRC ADDRESS STABLE tPRC ADDRESS STABLE tPRC ADDRESS STABLE tPRC ADDRESS STABLE tPRC ADDRESS STABLE ADDRESS STABLE ADDRESS STABLE (AN) (AN+1) (AN+2) (AN+3) (AN+4) (AN+5) (AN+6) (AN+7) VIH Page Address (A0 to A2) VIL SC-CE1 OE DOUT VIH VIL VIH VIL VOH VOL tCLOL tACE tAA tASO tOE tOLZ tPAA tOH VALID OUTPUT tCHAH tOH tCHZ tOHAH tPAA tOH VALID OUTPUT tCLZ tPAA tOH VALID OUTPUT tPAA tOH VALID OUTPUT tPAA tOH VALID OUTPUT tPAA tOH VALID OUTPUT tPAA tOH VALID OUTPUT tOHZ VALID OUTPUT (QN) (QN+1) (QN+2) (QN+3) (QN+4) (QN+5) (QN+6) (QN+7) Notes: 1. In read cycle, SC-CE2 and WE should be fixed to high level. 2. LB and UB are Low level. sharp Write Cycle Timing Chart 1 (SC-CE1 Controlled)) L R S1 8 3 0 50 tWC tWC Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tOHAH tOES ADDRESS STABLE tAS tCW tWR tCP ADDRESS STABLE tAS tCW tWR tCP tAS SC-CE1 WE UB LB OE tDW tDH tDW tDH DIN High - Z VALID INPUT VALID INPUT High - Z Notes: 1. During address transition, at least one of SC-CE1, WE or LB, UB pins should be inactivated. 2. Do not input data to the DQ pins while they are in the output state. 3. In write cycle, SC-CE2 and OE should be fixed to high level. 4. Write operation is done during the overlap time of a low level SC-CE1, WE, LB and/or UB. sharp Write Cycle Timing Chart 2 (WE Controlled)) L R S1 8 3 0 51 tWC tWC VIH Address VIL tCW tCHAH tCW tCHAH ADDRESS STABLE ADDRESS STABLE VIH SC-CE1 VIL tAS tWP tWR tCP tAS tWP tWR tCP VIH WE VIL VIH VIL VIH OE VIL tWHZ tOW tOHAH tOES tASO tOEH tWHP tBHAH tBHAH UB LB VOH DOUT VOL tDW tDH High - Z tDW tDH VIH DIN VIL High - Z VALID INPUT VALID INPUT High - Z Notes: 1. During address transition, at least one of SC-CE1, WE or LB, UB pins should be inactivated. 2. Do not input data to the DQ pins while they are in the output state. 3. In write cycle, SC-CE2 and OE should be fixed to high level. 4. Write operation is done during the overlap time of a low level SC-CE1, WE, LB and/or UB. sharp Write Cycle Timing Chart 3 (WE Controlled)) L R S1 8 3 0 52 tWC tWC VIH Address VIL tAW tAW ADDRESS STABLE ADDRESS STABLE VIH SC-CE1 VIL tAS tWP tWR tAS tWP tWR VIH WE VIL VIH VIL VIH OE VIL tWHZ tOW tOHAH tOES tASO tOEH tWHP tBHAH tBHAH UB LB VOH DOUT VOL tDW tDH High - Z tDW tDH VIH DIN VIL High - Z VALID INPUT VALID INPUT High - Z Notes: 1. During address transition, at least one of SC-CE1, WE or LB, UB pins should be inactivated. 2. Do not input data to the DQ pins while they are in the output state. 3. In write cycle, SC-CE2 and OE should be fixed to high level. 4. Write operation is done during the overlap time of a low level SC-CE1, WE, LB and/or UB. sharp Write Cycle Timing Chart 4 (LB / UB Controlled)) L R S1 8 3 0 53 tWC tWC Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tOHAH tOES ADDRESS STABLE ADDRESS STABLE SC-CE1 WE UB LB OE DIN tAS tBW tWR tBP tAS tBW tWR tBP tOEH tASO High - Z tDW tDH VALID INPUT tDW tDH VALID INPUT High - Z Notes: 1. During address transition, at least one of SC-CE1, WE or LB, UB pins should be inactivated. 2. Do not input data to the DQ pins while they are in the output state. 3. In write cycle, SC-CE2 and OE should be fixed to high level. 4. Write operation is done during the overlap time of a low level SC-CE1, WE, LB and/or UB. sharp L R S1 8 3 0 54 Write Cycle Timing Chart 5 (LB / UB Independent Controlled)) tWC tWC Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tOHAH tOES ADDRESS STABLE ADDRESS STABLE SC-CE1 WE tAS tBW tWR LB tAS tBP tBW tWR tASO UB tOEH OE DIN VIH (DQ0 to DQ7) VIL DIN VIH (DQ8 to DQ15) VIL High - Z tDW tDH VALID INPUT tDW tDH VALID INPUT High - Z Notes: 1. During address transition, at least one of SC-CE1, WE or LB, UB pins should be inactivated. 2. Do not input data to the DQ pins while they are in the output state. 3. In write cycle, SC-CE2 and OE should be fixed to high level. 4. Write operation is done during the overlap time of a low level SC-CE1, WE, LB and/or UB. sharp Mode Register Setting Timing Chart L R S1 8 3 0 55 tRC Mode Register Setting tRC tWC 1FFFFFH 1FFFFFH tWC Address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 1FFFFFH 1FFFFFH SC-CE1 OE tWP tWR tWP tWR WE tDW tDH tDW tDH DIN UB LB xxxxH xxxxH sharp Mode Register Setting Flow Chart L R S1 8 3 0 56 Start No Address = 1FFFFFH Read with toggled the SC-CE1, OE Address = 1FFFFFH Read with toggled the SC-CE1, OE Address = 1FFFFFH Write No No No Data = 00H? No Address = 1FFFFFH Write No Fail Mode register setting exit Data = 07H? End sharp Sleep Mode Entry / Exit Timing Chart L R S1 8 3 0 57 VIH SC-CE2 VIL tCHML tMHCL VIH SC-CE1 VIL Sleep Mode Standby Mode sharp 7. Notes L R S1 8 3 0 58 This product is a stacked CSP package that a 1 2 8 M (x 1 6 ) bit Flash Memory, a 128M (x16) bit Flash Memory and 32M (x16) bit Smartcombo RAM are assembled into. -Supply Power Maximum difference (between F1-VCC, F2-VCC and SC-VCC) of the voltage is less than 0.3V. -Power Supply and Chip Enable of Flash Memory, Smartcombo RAM Two or more chips among Flash memory (F1, F2), Smartcombo RAM should not be active simultaneously. If the two memories are active together, possibly they may not operate normally by interference noises or data collision on DQ bus. Both F1-VCC, F2-VCC and SC-VCC are needed to be applied by the recommended supply voltage at the same time except Smartcombo RAM sleep mode. -Power Up Sequence When turning on Flash memory power supply, keep F-RST low. After F1,F2-VCC reaches over 2.7V, keep F-RST low for more than 100 nsec. -Device Decoupling This is a 3 chips stacked CSP package. When one of the chips is active, others are in standby mode. Therefor, these power supplies should be designed very carefully. Exclusive power supply pins for each Memory and GND pin need careful decoupling of devices. Especially, note Flash Memory and Smartcombo RAM peak current caused by transition of control signals. When one of the Flash Memory is in busy mode, (page buffer) program, block erase and Bank erase command should not be inputted to the other (F1-CE, F2-CE, SC-CE1, SC-CE2). sharp 8. Flash Memory Data Protection L R S1 8 3 0 59 Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto WE signal or power supply, may be interpreted as false commands and causes undesired memory updating. To protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate: The below describes data protection method. 1. Protection of data in each block * ny locked block by setting its block lock bit is protected against the data alternation. When WP/ACC is low, any locked- down block by setting its block lock-down bit is protected from lock status changes. By using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked blocks). * For detailed block locking scheme, see Section 6.2 Command Definitions for Flash Memory. 2. Protection of data with F-RST * Especially during power transitions such as power-up and power-down, the flash memory enters reset mode by bringing F-RST to low, which inhibits write operation to all blocks. * For detailed description on F-RST control, see Section 6.6.6 AC Electrical Characteristics for Flash Memory, Reset Operations. Protection against noises on WE signal To prevent the recognition of false commands as write commands, system designer should consider the method for reducing noises on WE signal. sharp 9. Design Considerations 1. Power Supply Decoupling L R S1 8 3 0 60 To avoid a bad effect to the system by flash memory, Smartcombo RAM power switching characteristics, each device should have a 0.1F ceramic capacitor connected between VCC and GND, between WP/ACC and GND. Low inductance capacitors should be placed as close as possible to package leads. 2. WP/ACC Trace on Printed Circuit Boards Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the WP/ACC Power Supply trace. Use similar trace widths and layout considerations given to the VCC power bus. 3. The Inhibition of Overwrite Operation Please do not execute reprograming "0" for the bit which has already been programed "0". Overwrite operation may generate unerasable bit. In case of reprograming "0" to the data which has been programed "1". *Program "0" for the bit in which you want to change data from "1" to "0". *Program "1" for the bit which has already been programed "0". For example, changing data from "1011110110111101" to "1010110110111100" requires "1110111111111110" programing. 4. Power Supply Block erase, bank erase, (page buffer) program with an invalid WP/ACC (See Chapter 6.5 DC Electrical Characteristics for Flash Memory) produce spurious results and should not be attempted. Device operations at invalid VCC voltage (See Chapter 6.5 DC Electrical Characteristics for Flash Memory, 7.2 DC Electrical Characteristics for Smartcombo RAM) produce spurious results and should not be attempted. sharp L R S1 8 3 0 61 10. Related Document Information(1) Document No. FUM00701 Note: 1. International customers should contact their local SHARP or distribution sales offices. Document Name LH28F320BF, LH28F640BF, LH28F128BF Series Appendix sharp LRS1830 Flash MEMORY ERRATA 1. AC Characteristics i PROBLEM The table below summarizes the AC characteristics. AC Characteristics - Write Operations VCC=2.7V-3.1V Page 25 25 tAVAV tWHWL (tEHEL) Symbol Write Cycle Time F-WE (F-CE) Pulse Width High Parameter Min. 75 25 Max. Unit ns ns WORKAROUND System designers should consider these specifications. STATUS This is intended to be fixed in future devices. 021219 sharp B-1 POWER UP SEQUENCE OF Smartcombo RAM When turning on Smartcombo RAM power supply, the following sequence is needed. i B-1.1 Sequence of Smartcombo RAM Power Supply (1) Supply power. (2) Keep S-CE2 low longer than or equal to 50s. (See NOTES *1) (3) Keep S-CE1 and S-CE2 high longer than or equal to 300s. (See NOTES *2 ) (4) End of Initialization. By executing above (1) to (4), the initialization of chip inside and the power occurred inside become stable. from CPU S-CE1 S-CE2 VCC Combination Memory System Reset F-RST Add "300s (*2) wait routine" by software before the first Smartcombo RAM access. Need 10ns (Min.) S-CE1 VIH VIH (*1) VIL (*2) Need 50s (Min.) S-CE2 Need 300s (Min.) VIH 1st Access to Smartcombo RAM VCC VCC (Min.) NOTES: *1) Connect System Reset signal to S-CE2 and hold S-CE2 low longer than or equal to 50s. *2) By adding "300s Wait Routine" (S-CE1 and S-CE2 high) in the software, delay the first access to Smartcombo RAM longer than or equal to 300s. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 Fast Info: (1) 800-833-9437 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Corporation Electronic Components & Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221 Fax: (81) 6117-725300/6117-725301 www.sharp-world.com TAIWAN KOREA SHARP Electronic Components (Taiwan) Corporation 8F-A, No. 16, Sec. 4, Nanking E. Rd. Taipei, Taiwan, Republic of China Phone: (886) 2-2577-7341 Fax: (886) 2-2577-7326/2-2577-7328 SHARP Electronics (Singapore) PTE., Ltd. 438A, Alexandra Road, #05-01/02 Alexandra Technopark, Singapore 119967 Phone: (65) 271-3566 Fax: (65) 271-3855 SHARP Electronic Components (Korea) Corporation RM 501 Geosung B/D, 541 Dohwa-dong, Mapo-ku Seoul 121-701, Korea Phone: (82) 2-711-5813 ~ 8 Fax: (82) 2-711-5819 CHINA HONG KONG SHARP Microelectronics of China (Shanghai) Co., Ltd. 28 Xin Jin Qiao Road King Tower 16F Pudong Shanghai, 201206 P.R. China Phone: (86) 21-5854-7710/21-5834-6056 Fax: (86) 21-5854-4340/21-5834-6057 Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp SHARP-ROXY (Hong Kong) Ltd. 3rd Business Division, 17/F, Admiralty Centre, Tower 1 18 Harcourt Road, Hong Kong Phone: (852) 28229311 Fax: (852) 28660779 www.sharp.com.hk Shenzhen Representative Office: Room 13B1, Tower C, Electronics Science & Technology Building Shen Nan Zhong Road Shenzhen, P.R. China Phone: (86) 755-3273731 Fax: (86) 755-3273735 |
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